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Tech 060 REport.28516kInfoPrinter InfoDefault ATalk Zone InfoFileSharing InfoStartup Disk InfoVolumes InfoSystem Heap InHere is a message that might be of interest to some members. Please direct any replies to the author in the message header or to ALL ***** START OF CROSSPOSTED MESSAGE From: TOERNE@RHEIN IAM UNI-BONN Date: 05-24-93 04:33 To: ALL Msg#: 13975 Subj.: MOTOROLA 68060 FACTS ! Area: U-LIAMIGA Here it finally is: MOTOROLA SEMICONDUCTOR PRODUCT INFORMATION on the MC68060 (a really thing worth reading because this time it's not one's opinion but pure objective information from a reliable source - ;-)) ------------------------------------------------------------------------ 1 Product Brief Forth-Generation 32-Bit Microprocessor The MC 68060 is a superscalar, high-performance, 32-bit microprocessor providing a low-power mode of operation. The MC68060 is fully compatible with all previous members of the M68000 family. The MC68060 features dual on-chip caches, fully independent demand-paged memory management units (MMUs) for both instructions and data, dual integer execution pipelines, on-chip floating-point unit (FPU), and branch target cache. A high degree of instruction execution parallelism is achieved through the use of a full internal Havard architecture, multiple internal buses, independent execu- tion units, and dual instruction issue within the instruction execution controller. Power management is also a key part of the MC68060 architec- ture. The MC68060 offers a low-power mode of operation that is accessed through the LPSTOP instruction, allowing for full power-down capability. The MC68060 design is fully static so that when circuits are not in use, they do not draw power. Each unit can be disabled so that the power is used only when the unit is enabled and executing an instruction. Figure 1 illustrates a block diagram of the MC68060. +------------------------------------------+ +-+ |Integer unit | | | | +----------------------------+ | | | | |Instruction fetch controller| | | | | | +------+ +--------+ | | +----------------------------+ | | | | |Branch|<-| IA |----------->| +----------+ +----------+ | | | | | |Cache | |Generate| | | | |Intruction|->|Intruction| | | | | | | | +--------+ | | | | ATC | | Cache | | | | | | | |->|Intruct.|<-----------| +----------+ +----------+ | | | Intruct. | | | | | Fetch | | | | ^ ^ |<-| | Address | | +------+ +--------+ | | | | | | | |<-------> | | | Early | | | | +------------------+ | | | | | | Decode | | | | | Instruction | | | | | | +--------+ | | | | Cache | | | | | | | | | | | Controller | | | | | | V | | | +------------------+ | | | | | +------------------------+ | | +----------------------------+ | | | | | Instruction | | | |B| | | | Buffer | | | |U| | | +------------------------+ | | Diagram scribbled by |S| | | | | | | Christian von Toerne | | | +--------|---------|---------+ | toerne@rhein.iam.uni-bonn.de |C| | | | | |O| Data | +------------------|---------|---------+ | |N| Address | | V V | | |T|<-------> | | +--------+--------+ | | |R| | | +----------+ + Decode | Decode | | | |O| | | | Floating | +--------+--------+ | | +----------------------------+ |L| | | | Point | | EA | EA | | |<-| +------------------+ | |L| | | | Unit | |Generate|Generate| | | | | Data | | |E| | | | +------+ | +--------+--------+ | | | | Cache | | |R| | | | | EA | | | EA | EA | | | | | Controller | | | | | | | | Fetch| | | Fetch | Fetch | | | | +------------------+ | | | | | | +------+ | +--------+--------+ | | | | | |<>| | | | | | FP | | | INT | INT | | |->| V V | | | | | | | Exec | | | Execute| Execute| | | | +----------+ +----------+ | | | | | | +------+ | +--------+--------+ | | | | Data |->| Data | | | | | | +----|-----+ Instruction | | | | ATC | | Cache | | | | | | | Execution Controller | | | +----------+ +----------+ | | | | +------|------------|--------|---------+ | +----------------------------+ | | Control | V V V | ^ | |<-------> | +--------------------------------------+ | | | | | | Data available | | | | | | +--------------------------------------+ | | | | | | Write-Back | | | | | | +--------------------------------------+ | | | | +------------------------------------------+ | +-+ | Operand data bus | +--------------------------------------+ Figure 1. MC68060 Simplified Block Diagram (This document contains information on a product under develoment. Motoro- la reserves the right to change or discontinue this product without no- tice.) ------------------------------------------------------------------------ 2 Complete code compatibility with the M68000 family allows the designer to draw on existing code and past experience to bring products to market quickly. There is also a broad base of established development tools, in- cluding real-time kernels, operating systems, languages, and applications, to assist in product design. The functionality provided by the MC68060 makes is the ideal choice for a range of high-performance computing appli- cations as well as many portable application that require low power and high performance. The MC68060's high level of integration results in high performance while reducing overall system power consumption. The following is a list of primary features for the MC68060: - 100% User-Mode Compatible with MC68040 - Three Times the Performance of a 25-MHz MC68040 - Superscalar Implementation of M68000 Architecture - Dual Integer Instruction Execution Improves Performance - IEEE-Compatible On-Chip FPU - Branch Target Cache Minimizes Branch Latency - Independent Instruction and Data MMUs - Dual 8-Kbyte On-Chip Caches -- Seperate Data and Instruction Caches -- Simultaneous Access - Bus Snooping - Full 32-Bit Nonmultiplexed Address and Data Bus -- 32-Bit Bus Maximizes Data Throughput -- Nonmultiplexed Bus Simplifies Design -- Four-Deep Write Buffer to Maximize Write Bandwidth -- MC68040-Compatible Bus Provides Simple Hardware Migration Path - Concurrent Operation of Integer Unit, MMUs, Caches, Bus Controller, Integer Pipelines, an FPU Provides High Performance - Power Consumption Control -- Static HCMOS Technology Reduces Power in Normal Operation -- Low-Voltage Operation at 3.3 V -- LPSTOP Provides an Idle State for Lowest Standby Current - 50 MHz and 66 MHz - Packaging -- Ceramic Pin Grid Array (PGA) -- Ceramic Quad Flat Pack (CQFP) ------------------------------------------------------------------------ 3 MC68060 Signals +-------------+ Processor ---- _CDIS --> | | ---- _BR ----> Control ---- _MDIS --> | | <--- _BG ----- Bus Arbitration | | <--- _BB ----> Control Snoop | | <--- _BGR ---- Control ---- SNOOP --> | | <--- _BTT ---> | | <--- TT0 ----> | | ---- PST0 ---> <--- TT1 ----> | | ---- PST1 ---> Processor <--- TM0 ----- | | ---- PST2 ---> Status <--- TM1 ----- | | ---- PST3 ---> <--- TM2 ----- | | ---- PST4 ---> <--- TLN0 ---- | | <--- TLN1 ---- | | <--- _IPL0 --- <--- UPA0 ---- | | <--- IPL1 ---- <--- UPA1 ---- | | <--- _IPL2 --- Interrupt Transfer <--- R/_W ---- | MC68060 | ---- _IPEND -> Control Attributes <--- SIZ0 ---- | | <--- _AVEC --- <--- SIZ1 ---- | | <--- _LOCK --- | | <--- CLK ----- Clock and <--- _LOCKE -- | | <--- _CLKEN -- Control <--- _CIOUT -- | | <--- _BS0 ---- | | ---- _RSTO --> Reset <--- _BS1 ---- | | <--- _RSTI --- <--- _BS2 ---- | | <--- _BS3 ---- | | // A31 \\ Address Port | | \\ - A0 // and Control Master <--- _TS ----> | | <--- _CLA ---- Transfer <--- _TIP ---- | | Control <--- _SAS ---- | | // D31 \\ Data Port | | \\ - D0 // Slave ---- _TA ----> | | Transfer ---- _TEA ---> | | <-/- TEST ---- Test Interface Control ---- _TCI ---> | | ---- _TRA ---> | | <-/- Vcc ----- Power and | | <-/- GND ----- Ground +-------------+ Figure 2. Funtional Signal Groups INTEGER UNIT The MC68060's integer unit carries out logical and arithmetic operations. The integer unit contains an instruction fetch controller, an execution controller, and a branch target cache. The superscalar design of the MC68060 provides dual execution pipelines in the intruction execution controller, providing simultaneous execution. The superscalar operation of the integer unit can be disabled in software, turning off the second executionpipeline for debugging. Disabling the superscalar operation also lowers power consumption. ------------------------------------------------------------------------ 4 INSTRUCTION FETCH CONTROLLER The intruction fetch controller contains an instruction fetch pipeline and the logic that interfaces to the branch target cache. The instruction fetch pipeline consists of four stages, providing the ability to prefetch instructions in advance of their actual use in the instruction cache con- troller. The continous fetching of instructions kepps the instruction ex- excution controller busy for the greatest possible performance. Every in- struction passes through each of the four stages before entering the in- struction execution controller. The four stages in the instruction fetch pipeline are: 1. Instruction Address Calculation -- The virtual address of the instruc- tion is determined. 2. Instruction Fetch -- The instruction is fetched from memory. 3. Early Decode -- The instruction is pre-decoded for pipeline control information. 4. Instruction Buffer -- The instruction and its pipeline control infor- mation are buffered until the integer execution pipeline is ready to process the instruction. BRANCH TARGET CACHE The branch target cache plays the major role in achieving the performance levels of the MC68060. The concept of the branch target cache is to pro- vide a mechanism that allows the instruction fetch pipeline to detect and change the instruction stream before the change of flow affects the in- struction execution controller. The branch target cache is examined for a valid branch entry after each instruction fetch address is generated in the intruction fetch pipeline. If a hit does not occur in the branch target cache, the instruction fetch pipeline continues to fetch instructions sequentially. If a hit occurs in the branch target cache, indicating a branch taken instruction, the cur- rent instruction stream is discarded and a new instruction stream is fetched starting at the location indicated by the branch target cache. INSTRUCTION EXECUTION CONTROLLER The instruction execution controller contains dual integer execution pipe- lines, interface logic to the FPU, and control logic for data written to the data cache and MMU. The superscalar design of the dual integer execu- tion pipeline provide for simultaneous instruction execution, which allows the processing more than one instruction during each machine clock cycle. The net effect of this is a software invisible pipeline capable of sus- tained execution rates of less than on machine clock cycle per instruction for the MC68060 instruction set. The instruction execution controller's control logic pulls an intruction pair from the instruction buffer every machine clock cycle, stopping only if the instruction information is not available or if an integer execution hold condition exists. The six stages in the dual integer execution pipe- lines are: 1. Instruction decode -- The instruction is fully decoded. 2. Effective address calculation -- If the instruction calls for data from memory, the location of the data is calculated. 3. Effective address fetch -- Data is fetched from the memory location. 4. Integer execution -- The data is manipulated during the execution. 5. Data available -- The result is available. 6. Write-Back -- The resulting data is written back to on-chip caches or external memory. The MC68060 if optimized for most integer instructions to execute in one machine clock cycle. If during the instruction decode stage, the instruc- tion is determined to be a floating-point instruction, it will be passed to the FPU after the effective address fetch stage. If data is to be written to either the on-chip caches or external memory after instruction ------------------------------------------------------------------------ 5 execution, the write-back stage holds the data until memory is ready to receive it. Temporarily holding data in the write-back stage adds to the overall performance of the MC68060 by not slowing down pipeline opera- tions. FLOATING-POINT UNIT Floating-point is distinguished from integer math, which deals only with whole numbers and fixed decimal point locations. The IEEE-compatible MC68060's FPU computes numeric calculations with a variable decimal point locationThe MC68060 features a built-in FPU that is MC68040 and MC68881/82 compatible. Consolidating this important function on-chip speeds up over- all processing and eliminates interfacing overhead associated with exter- nal accelerators. The MC68060's FPU operates in parallel with the integer unit. The FPU performs numeric calculations while the integer unit conti- nues integer processing. The FPU has been optimized for the most frequently used instructions and data types to provide the highest possible performance. The FPU can also be disabled in software to reduce system power consumption. FLOATING POINT EMULATION The MC68060 implements the most frequently M68000 family floating-point instructions, data-types, and data formats in hardware for the highest performance. T he remaining instructions are emulated in software with the M68060FPSP to provide complete IEEE compatibility. The MC68060FPSP pro- vides the following features: - Arithmetic and Transcendental Instructions - IEEE-Compliant Exception Handlers - Unimplemented Data Type and Data Format Handlers MEMORY MANAGEMENT UNITS The MC68060 contains independent instruction and data MMUs. Each MMU con- tains a cache memory called the address translation cache (ATC). The full addressing range of the MC68060 is 4 Gbytes (4,294,967,296 bytes). Even though most MC68060 systems implement a much smaller physical memory, by using virtual memory techniques, the system can appear to have a full 4 Gbytes of physical memory available to each user program. Each MMU fully supports demand-paged virtual-memory systems with either 4- or 8-Kbyte page sizes. Each MMU protects supervisor areas from accesses by user pro- grams and provides write-protection on a page-by-page basis. For maximum efficiency, each MMU operates in parallel with other processor activities. The MMUs can be disabled for emulator and debugging support. ADDRESS TRANSLATION The 64-entry, four-way, set-associative ATCs store recently used logical- to-physical address translation information as page descriptors for in- struction and data accesses. Each MMU initiates address translation by searching for a descriptor containing the address translation information in the ATC. If the descriptor does not reside in the ATC, the MMU performs external bus cycles through the bus controller to search the translation tables in physical memory. After being located, the page descriptor is loaded into the ATC, and the address is correctly translated for the ac- cess. ------------------------------------------------------------------------ 6 INSTRUCTION AND DATA CACHES Studies have shown that typical programs spend much of their execution time in a few main routines of tight loops. Earlier members of the M68000 family took advantage of this locality-of-reference phenomenon to varying degrees. The MC68060 takes further advantage of cache technology with its two, independent, on-chip physical chaches, one for instruction and one for data. The caches reduce the processor's external bus activity and in- crease CPU throughput by lowering the effective memory access time. For a typical system designm the large caches of the MC68060 yield a hery high hit rate, providing a substantial increase in system performance. The autonomous nature of the caches allows intruction-stream fetches, data-stream fetches, and external accesses to occur simultaneously with instruction execution. For example, if the MC68060 requires both an in- struction access and an external peripheral access and if the instruction is resident in the in-chip cache, the periphal access proceeds umimpeded rather than being queued behind the instruction fetch. If a data operand is also required and it is resident in the data cache, it can be accessed without hindering either the instruction access or the external periphal access. The parallelism inherent on the MC68060 also allows multiple in- structions that do not require any external accesses to execute concur- rently while the processor is performing an external access for a previous instruction. Each MC68060 cache is 8 Kbytes, accessed by physical addresses. The data can be configured as write-through or deferred copyback on a page-basis. This choice allows for optimizing the system design for the high perfor- mance if deferred copyback is used. Cachability of data in each memory page is controlled by two bits in the page descriptor. Cachable pages can be either write-through or copyback, with no write-allocate for misses to write-through pages. The MC68060 implements a four-entry write buffer that maximizes system performance by decoupling the integer pipeline from the external system bus. When needed, the write buffer allows the pipeline to generate writes every clock cycle, even if the system bus runs at a slower speed than the processor. CACHE ORGANIZATION The instruction and data caches are each organized as 4-way set associa- tive, with 16-bite lines. Each line of data has associated with it an ad- dress tag and state information that shows the line's validity. In the data cache, the state information indicates wheter the line is invalid, valid, or dirty. CACHE COHERENCY The MC68060 has the ability to watch or snoop the external bus during ac- cesses by other bus masters, maintaining coherency between the MC68060's caches and external memory systems. External bus cycles can be flagged on the bus as snoopable or nonsnoopable. When an external cycle is marked as snopable, the bus snooper checks the caches and invalidates the matching data. Although the integer execution units and the bus snooper circuit have access to the on-chip caches, the snooper has priority over the exec- ution units. BUS CONTROLLER The bus is implemented as a nonmultiplexed, fully synchronous protocol that is clocked off the rising edge of the input clock. The bus controller operates concurrently with all other functional units of the MC68060 to maximize system throughput. The timing of the bus is fully configurable to match external memory requirements. ------------------------------------------------------------------------ 7 IEEE 1149.1 TEST To aid the system diagnostics, the MC68060 includes dedicated user-access- ible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testablility, ofter referred to as Joint Test Action Group (JTAG). POWER CONSUMPTION MANAGEMENT The MC68060 is very power efficient due to the static logic and power management designed into the basic architecture. Each stage of the integer unit pipelines and the FPU pipeline draws power only when an instruction is executing, and the cache arrays draw power only when an access is made. The FPU, secondary integer execution pipeline, branch target cache, and instruction and data caches can be disabled to reduce overall power us- age. The 3.3-V power supply reduces current consumption by 40-60% over that of microprocessors using a 5-V power supply. The MC68060 has additional methods for dynamically controlling power con- sumption during operation. Running a special LPSTOP instruction shuts down the active circuits in the processor, halting intruction execution. Power consumption in this standby mode is greatly reduced. Processing and power consumption can be resumed by resetting the processor or by generating an interrupt. The frequency of operation can be lowered to reduce current consumtion while the device is in LPSTOP mode. PHYSICAL The MC68060 will be available as 50 MHz and 66 MHz versions, with 3.3-V supply voltage, an in ceramic PGA and CQFP packaging configurations. The documents listed in the following table contain detailed information on the MC68060. These documents may be obtained from the Literature Di- stribution Centers at the addresses listed on the back page. Documentation +----------------------------+---------------+---------------------------+ | Document title | Order Number | Contents | +============================+===============+===========================+ | MC68060 User's manual | MC68060UM/AD* | Detailed information for | | | | Design | +----------------------------+---------------+---------------------------+ | M68000 Damily Programmer's | M68000PM/AD | M68000 Family Instruction | | Reference Manual | | Set | +----------------------------+---------------+---------------------------+ | The 68K source | BR729/D | Independent Vendor Listing| | | | Supporting Software and | | | | Development Tools | +----------------------------+---------------+---------------------------+ * Estimated availability is 3Q93. ------------------------------------------------------------------------ 8 +------------------------------------------------------------------------+ | Motorola reserves the right to make changes without furter notice to | | any products herein. Motorola makes no warranty, representation or | | guarantee regarding the suitability if its products for any particular | | purpose, nor does Motorola assume any liability arising out of the ap- | | plication or use of any product or circuit, and specially disclaims | | any and all liability, including without limitation consequential or | | incidential damages. "Typical" parameters can and do vary in different | | applications. All operating parameters, including "Typicals" must be | | validated for each customer application by customer's technical ex- | | perts. Motorola does not convey any license under its patent rights | | nor the rights of others. Motorola products are not designed, in- | | tended, or authorized for use as components in systems intended for | | surgical implant into the body, or other applications intended to sup- | | port or sustain life, or for any other application in which the fail- | | ure of the Motorola product could create a situation where personal | | injury or death may occur. Should Buyer purchase or use Motorola pro- | | ducts for any such unintended or unauthorized application, buyer shall | | indemnify and hold Motorola and its officers, employees, subsidiaries, | | affilates, and distributers harmless against all claims, costs, dam- | | ages, and expenses, and reasonable attorney fees arising out of, di- | | rectly or indirectly, any claim of personal injury or death assosiated | | with such unintended or unauthorized use, even if such claim alleges | | the Motorola was neglient regarding the design or manufacture of the | | part. Motorola and ____ are registered trademarks of Motorola, Inc. | | Motorola, Inc. is an Equal Opportunity / Affirmative Action Employer. | +------------------------------------------------------------------------+ Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. EUROPE: Motorola LTD.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. -------------------------------------------------------------------------- Information sheets hacked in on 23rd of May, 1993 by Christian von Toerne. -------------------------------------------------------------------------- -- cut here -- cut here -- cut here -- cut here -- cut here -- cut here -- That was the COMPLETE information on the MC68060. Nothing's been changed by me nor by any other person. Please, if you spread this file, don't kill the notice that this file was written by me. It took me 3 hrs. of enormous work, because my friend's scanner wasn't able to cope with the figures and the different text sizes. Comments, spelling mistakes a.s.o. to the list or to my personal account. Much fun reading this sheet, Christian von Toerne PS: In Figure 2 (Functional signal groups), _xxx means: ___ xxx ... OK ? PPS: It may be that Figure 1 is too wide ... well I cannot help it ! +-------------------------------------+--------------------------+ | Christian von Toerne | "Ich bin einer, der viel | | SMail: Am Burggraben 78, 53121 Bonn | gegruebelt, aber nichts | | VMail: +49-(0)228-616523 | gelernt hat!" | | EMail: toerne@rhein.iam.uni-bonn.de | | | -> Everything located in Germany <- | Albert Einstein | +-------------------------------------+--------------------------+ ***** END OF CROSSPOSTED MESSAGE Regards Charles